1. Field of the Invention
The present invention relates to a flash memory device and a method of manufacturing the same.
2. Description of the Related Art
In general, a flash memory device includes the advantages of EPROM having programming and erasing characteristics and EEPROM having electrically programming and erasing characteristics. This kind of flash memory device generally includes a thin tunnel oxide layer formed on a silicon substrate, a floating gate integrated on the oxide layer, an insulating layer, a control gate, and source and drain regions formed on the exposed portion of the substrate, in order to accomplish 1-bit storage using one transistor and to implement electrical programming and erasing.
Such a flash memory device may include a source connecting layer for connecting the source of each unit cell to form a source line. The source connecting layer can be formed by using a metal contact method by which a contact is formed in the source of each unit cell. However, this method is not appropriate for the manufacture of a highly integrated device because a contact margin should be considered. Therefore, recently, a common source line formed as an impurity diffusion layer through a self aligned source (SAS) process has been used to realize a highly integrated device.
In detail, the SAS process includes to an anisotropic etching process, in which a source region of a cell is opened by using a separate SAS mask after forming a gate electrode having a stacked structure, and then removing a field oxide layer to form a common source line relative to a neighboring cell.
Such an SAS technique may shrink the size of a cell in the bit line (BL) direction, and so the gate to source space can be reduced. Therefore, this technique is a useful process for accomplishing a device having a line width of 0.25 μm level.
Impurity ions such as arsenic (As) are implanted with high energy so as to form a junction having a predetermined depth on the common source line formed through the SAS process.
However, since the common source line is formed along the profile of a trench in a memory cell formed through the SAS process, the contact resistance of the source per cell is rapidly increased, in practice. This is because the length of the real surface resistance is increased due to the junction resistance formed along the surface profile of the trench region, so the specific resistance of the sidewall of the trench region is increased. That is, a relatively small amount of ions are implanted into the sidewall portion of the trench region during the ion implantation process, so the resistance may increase significantly.
In particular, most memory cells having a line width of at least or about 0.25 μm or 0.18 μm employ a shallow trench isolation (STI) process as an isolation technique. The STI process can be a useful process to shrink the size of the cell along a word line (WL) direction, while the SAS process is essential to shrink the cell size along a bit line (BL) direction, depending on the orientation of the word lines and bit lines. However, if these processes are simultaneously applied, the source resistance can be remarkably increased.
Since flash memory devices generally utilize an internal high voltage for programming and/or erasing operations, when the cell size is decreased, the depth of the trench should be increased, resulting in an increase in the length of the common source line, in turn adversely affecting the source resistance. In the case of an embedded flash memory device, potentially fatal product defects including degradation of programming characteristics and reading speed may result.
Meanwhile, since the impurity ions are implanted with high energy, the surface of the common source line can be damaged, further increasing a surface resistance, thereby deteriorating the characteristics of a resulting semiconductor device.